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<!@TC:1415277446>
#Build: Synplify Pro I-2014.03L-SP1 , Build 045R, Jul 30 2014
#install: C:\lscc\diamond\3.3_x64\synpbase
#OS: Windows 7 6.1
#Hostname: L27738

#Implementation: syn_results

<a name=compilerReport1>Synopsys Verilog Compiler, version comp201403sp1p1, Build 043R, built Jul 30 2014</a>
@N: : <!@TM:1415277446> | Running in 64-bit mode 
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@I::"C:\lscc\diamond\3.3_x64\synpbase\lib\lucent\ecp5um.v"
@I::"C:\lscc\diamond\3.3_x64\synpbase\lib\lucent\pmi_def.v"
@I::"C:\lscc\diamond\3.3_x64\synpbase\lib\vlog\umr_capim.v"
@I::"C:\lscc\diamond\3.3_x64\synpbase\lib\vlog\scemi_objects.v"
@I::"C:\lscc\diamond\3.3_x64\synpbase\lib\vlog\scemi_pipes.svh"
@I::"C:\lscc\diamond\3.3_x64\synpbase\lib\vlog\hypermods.v"
@I::"C:\lscc\diamond\3.3_x64\cae_library\synthesis\verilog\ecp5um.v"
@I::"C:\lscc\diamond\3.3_x64\cae_library\synthesis\verilog\pmi_def.v"
@I::"D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.v"
@N:<a href="@N:CG346:@XP_HELP">CG346</a> : <a href="D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.v:143:36:143:45:@N:CG346:@XP_MSG">ip_gddr71rx.v(143)</a><!@TM:1415277446> | Read full_case directive 
@N:<a href="@N:CG347:@XP_HELP">CG347</a> : <a href="D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.v:143:46:143:59:@N:CG347:@XP_MSG">ip_gddr71rx.v(143)</a><!@TM:1415277446> | Read parallel_case directive 
<font color=#A52A2A>@W:<a href="@W:CG286:@XP_HELP">CG286</a> : <a href="D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.v:143:2:143:6:@W:CG286:@XP_MSG">ip_gddr71rx.v(143)</a><!@TM:1415277446> | Case statement has both a full_case directive and a default clause -- ignoring full_case directive.</font>
Verilog syntax check successful!
File D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.v changed - recompiling
Selecting top level module ip_gddr71rx
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.v:30:7:30:27:@N:CG364:@XP_MSG">ip_gddr71rx.v(30)</a><!@TM:1415277446> | Synthesizing module ip_gddr71rxgddr_sync

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.3_x64\cae_library\synthesis\verilog\ecp5um.v:278:7:278:9:@N:CG364:@XP_MSG">ecp5um.v(278)</a><!@TM:1415277446> | Synthesizing module IB

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.3_x64\cae_library\synthesis\verilog\ecp5um.v:1633:7:1633:14:@N:CG364:@XP_MSG">ecp5um.v(1633)</a><!@TM:1415277446> | Synthesizing module IDDR71B

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.3_x64\cae_library\synthesis\verilog\ecp5um.v:1534:7:1534:14:@N:CG364:@XP_MSG">ecp5um.v(1534)</a><!@TM:1415277446> | Synthesizing module CLKDIVF

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.3_x64\cae_library\synthesis\verilog\ecp5um.v:1558:7:1558:16:@N:CG364:@XP_MSG">ecp5um.v(1558)</a><!@TM:1415277446> | Synthesizing module ECLKSYNCB

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.3_x64\cae_library\synthesis\verilog\ecp5um.v:761:7:761:10:@N:CG364:@XP_MSG">ecp5um.v(761)</a><!@TM:1415277446> | Synthesizing module VLO

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.3_x64\cae_library\synthesis\verilog\ecp5um.v:1696:7:1696:14:@N:CG364:@XP_MSG">ecp5um.v(1696)</a><!@TM:1415277446> | Synthesizing module EHXPLLL

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.v:215:7:215:18:@N:CG364:@XP_MSG">ip_gddr71rx.v(215)</a><!@TM:1415277446> | Synthesizing module ip_gddr71rx

@END

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 76MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Nov 06 18:07:26 2014

###########################################################]
Synopsys Netlist Linker, version comp201403sp1p1, Build 043R, built Jul 30 2014
@N: : <!@TM:1415277448> | Running in 64-bit mode 
File D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\syn_results\synwork\ip_gddr71rx_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Nov 06 18:07:28 2014

###########################################################]
Pre-mapping Report

<a name=mapperReport2>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 987R, Built Aug  4 2014 10:41:06</a>
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03L-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Reading constraint file: D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.fdc
Linked File: <a href="D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\syn_results\ip_gddr71rx_scck.rpt:@XP_FILE">ip_gddr71rx_scck.rpt</a>
Printing clock  summary report in "D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\syn_results\ip_gddr71rx_scck.rpt" file 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1415277448> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1415277448> | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
ICG Latch Removal takes time: 0.000000 [s]. 
syn_allowed_resources : blockrams=56  set on top level netlist ip_gddr71rx


<a name=mapperReport3>@S |Clock Summary</a>
****************

Start                    Requested     Requested     Clock        Clock              
Clock                    Frequency     Period        Type         Group              
-------------------------------------------------------------------------------------
System                   1.0 MHz       1000.000      system       system_clkgroup    
ip_gddr71rx|sync_clk     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
=====================================================================================

<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="d:\rd_work_area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.v:95:0:95:6:@W:MT529:@XP_MSG">ip_gddr71rx.v(95)</a><!@TM:1415277448> | Found inferred clock ip_gddr71rx|sync_clk which controls 12 sequential elements including Inst_gddr_sync.cs_gddr_sync[2:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Nov 06 18:07:28 2014

###########################################################]
Map & Optimize Report

<a name=mapperReport4>Synopsys Lattice Technology Mapper, Version maplat, Build 987R, Built Aug  4 2014 10:41:06</a>
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03L-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1415277451> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1415277451> | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)


Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------


Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1415277451> | The option to pack flops in the IOB has not been specified  

Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)



<a name=clockReport5>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>

1 non-gated/non-generated clock tree(s) driving 12 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=================================== Non-Gated/Non-Generated Clocks ===================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance               
------------------------------------------------------------------------------------------------------
<a href="@|S:sync_clk@|E:Inst_gddr_sync.cs_gddr_sync[2]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001  @XP_NAMES_BY_PROP">ClockId0001 </a>       sync_clk            port                   12         Inst_gddr_sync.cs_gddr_sync[2]
======================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\syn_results\ip_gddr71rx.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 140MB)

Writing Analyst data base D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\syn_results\synwork\ip_gddr71rx_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 140MB)

Writing EDIF Netlist and constraint files
I-2014.03L-SP1 
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1415277451> | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)

Writing Verilog Simulation files

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)

Writing VHDL Simulation files

Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 144MB)

<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="d:\rd_work_area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.v:361:12:361:25:@W:MT246:@XP_MSG">ip_gddr71rx.v(361)</a><!@TM:1415277451> | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="d:\rd_work_area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.v:325:14:325:29:@W:MT246:@XP_MSG">ip_gddr71rx.v(325)</a><!@TM:1415277451> | Blackbox ECLKSYNCB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="d:\rd_work_area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.v:320:12:320:25:@W:MT246:@XP_MSG">ip_gddr71rx.v(320)</a><!@TM:1415277451> | Blackbox CLKDIVF is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="d:\rd_work_area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.v:303:12:303:26:@W:MT246:@XP_MSG">ip_gddr71rx.v(303)</a><!@TM:1415277451> | Blackbox IDDR71B is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1415277451> | Found inferred clock ip_gddr71rx|sync_clk with period 10.00ns. Please declare a user-defined clock on object "p:sync_clk"</font> 



<a name=timingReport6>@S |##### START OF TIMING REPORT #####[</a>
# Timing Report written on Thu Nov 06 18:07:31 2014
#


Top view:               ip_gddr71rx
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\ip_gddr71rx.fdc
                       
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1415277451> | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1415277451> | Clock constraints cover only FF-to-FF paths associated with the clock. 



<a name=performanceSummary7>Performance Summary </a>
*******************


Worst slack in design: 7.058

@N:<a href="@N:MT286:@XP_HELP">MT286</a> : <!@TM:1415277451> | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
                         Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock           Frequency     Frequency     Period        Period        Slack     Type         Group              
---------------------------------------------------------------------------------------------------------------------------
ip_gddr71rx|sync_clk     100.0 MHz     339.8 MHz     10.000        2.942         7.058     inferred     Inferred_clkgroup_0
System                   100.0 MHz     868.1 MHz     10.000        1.152         8.848     system       system_clkgroup    
===========================================================================================================================





<a name=clockRelationships8>Clock Relationships</a>
*******************

Clocks                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------------------
Starting              Ending                |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------------
System                System                |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
System                ip_gddr71rx|sync_clk  |  10.000      8.848   |  No paths    -      |  No paths    -      |  No paths    -    
ip_gddr71rx|sync_clk  System                |  10.000      8.805   |  No paths    -      |  No paths    -      |  No paths    -    
ip_gddr71rx|sync_clk  ip_gddr71rx|sync_clk  |  10.000      7.058   |  No paths    -      |  No paths    -      |  No paths    -    
===================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo9>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport10>Detailed Report for Clock: ip_gddr71rx|sync_clk</a>
====================================



<a name=startingSlack11>Starting Points with Worst Slack</a>
********************************

                                   Starting                                                         Arrival          
Instance                           Reference                Type        Pin     Net                 Time        Slack
                                   Clock                                                                             
---------------------------------------------------------------------------------------------------------------------
Inst_gddr_sync.ctrl_cnt[3]         ip_gddr71rx|sync_clk     FD1S3DX     Q       ctrl_cnt[3]         1.015       7.058
Inst_gddr_sync.ctrl_cnt[0]         ip_gddr71rx|sync_clk     FD1S3DX     Q       ctrl_cnt[0]         1.009       7.064
Inst_gddr_sync.ctrl_cnt[1]         ip_gddr71rx|sync_clk     FD1S3DX     Q       ctrl_cnt[1]         0.985       7.088
Inst_gddr_sync.ctrl_cnt[2]         ip_gddr71rx|sync_clk     FD1S3DX     Q       ctrl_cnt[2]         0.955       7.117
Inst_gddr_sync.cs_gddr_sync[0]     ip_gddr71rx|sync_clk     FD1P3DX     Q       stop                1.027       7.131
Inst_gddr_sync.cs_gddr_sync[1]     ip_gddr71rx|sync_clk     FD1P3DX     Q       cs_gddr_sync[1]     1.015       7.143
Inst_gddr_sync.cs_gddr_sync[2]     ip_gddr71rx|sync_clk     FD1P3DX     Q       ready               1.039       7.771
Inst_gddr_sync.reset_flag          ip_gddr71rx|sync_clk     FD1P3DX     Q       reset_flag          1.015       7.803
Inst_gddr_sync.stop_assert[2]      ip_gddr71rx|sync_clk     FD1S3DX     Q       stop_assert[2]      0.955       7.893
Inst_gddr_sync.stop_assert[0]      ip_gddr71rx|sync_clk     FD1S3DX     Q       stop_assert[0]      0.907       7.941
=====================================================================================================================


<a name=endingSlack12>Ending Points with Worst Slack</a>
******************************

                                   Starting                                                               Required          
Instance                           Reference                Type        Pin     Net                       Time         Slack
                                   Clock                                                                                    
----------------------------------------------------------------------------------------------------------------------------
Inst_gddr_sync.reset_flag          ip_gddr71rx|sync_clk     FD1P3DX     SP      reset_flag_1_sqmuxa_i     9.806        7.058
Inst_gddr_sync.ctrl_cnt[0]         ip_gddr71rx|sync_clk     FD1S3DX     D       ctrl_cnt_3[0]             9.946        7.065
Inst_gddr_sync.ctrl_cnt[1]         ip_gddr71rx|sync_clk     FD1S3DX     D       ctrl_cnt_3[1]             9.946        7.065
Inst_gddr_sync.ctrl_cnt[2]         ip_gddr71rx|sync_clk     FD1S3DX     D       ctrl_cnt_3[2]             9.946        7.065
Inst_gddr_sync.ctrl_cnt[3]         ip_gddr71rx|sync_clk     FD1S3DX     D       ctrl_cnt_3[3]             9.946        7.065
Inst_gddr_sync.cs_gddr_sync[0]     ip_gddr71rx|sync_clk     FD1P3DX     D       N_120_i                   9.946        7.197
Inst_gddr_sync.cs_gddr_sync[1]     ip_gddr71rx|sync_clk     FD1P3DX     D       N_131                     9.946        7.803
Inst_gddr_sync.stop_assert[1]      ip_gddr71rx|sync_clk     FD1S3DX     D       stop_assert_4[1]          9.946        7.833
Inst_gddr_sync.stop_assert[2]      ip_gddr71rx|sync_clk     FD1S3DX     D       stop_assert_4[2]          9.946        7.833
Inst_gddr_sync.cs_gddr_sync[2]     ip_gddr71rx|sync_clk     FD1P3DX     D       N_145                     9.946        7.881
============================================================================================================================



<a name=worstPaths13>Worst Path Information</a>
<a href="D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\syn_results\ip_gddr71rx.srr:srsfD:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\syn_results\ip_gddr71rx.srs:fp:22018:23302:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.194
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.806

    - Propagation time:                      2.749
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     7.057

    Number of logic level(s):                3
    Starting point:                          Inst_gddr_sync.ctrl_cnt[3] / Q
    Ending point:                            Inst_gddr_sync.reset_flag / SP
    The start point is clocked by            ip_gddr71rx|sync_clk [rising] on pin CK
    The end   point is clocked by            ip_gddr71rx|sync_clk [rising] on pin CK

Instance / Net                                          Pin      Pin               Arrival     No. of    
Name                                       Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
Inst_gddr_sync.ctrl_cnt[3]                 FD1S3DX      Q        Out     1.015     1.015       -         
ctrl_cnt[3]                                Net          -        -       -         -           6         
Inst_gddr_sync.ns_gddr_sync16              ORCALUT4     D        In      0.000     1.015       -         
Inst_gddr_sync.ns_gddr_sync16              ORCALUT4     Z        Out     0.738     1.753       -         
ns_gddr_sync16                             Net          -        -       -         -           4         
Inst_gddr_sync.ns_gddr_sync_0_sqmuxa_3     ORCALUT4     B        In      0.000     1.753       -         
Inst_gddr_sync.ns_gddr_sync_0_sqmuxa_3     ORCALUT4     Z        Out     0.606     2.359       -         
ns_gddr_sync_0_sqmuxa_3                    Net          -        -       -         -           1         
Inst_gddr_sync.reset_flag_1_sqmuxa_i       ORCALUT4     B        In      0.000     2.359       -         
Inst_gddr_sync.reset_flag_1_sqmuxa_i       ORCALUT4     Z        Out     0.390     2.749       -         
reset_flag_1_sqmuxa_i                      Net          -        -       -         -           1         
Inst_gddr_sync.reset_flag                  FD1P3DX      SP       In      0.000     2.749       -         
=========================================================================================================




====================================
<a name=clockReport14>Detailed Report for Clock: System</a>
====================================



<a name=startingSlack15>Starting Points with Worst Slack</a>
********************************

                    Starting                                           Arrival           
Instance            Reference     Type          Pin       Net          Time        Slack 
                    Clock                                                                
-----------------------------------------------------------------------------------------
Inst1_EHXPLLL       System        EHXPLLL       LOCK      lock_chk     0.000       8.848 
Inst1_EHXPLLL       System        EHXPLLL       CLKOP     clkop        0.000       10.000
Inst1_EHXPLLL       System        EHXPLLL       CLKOS     clkos        0.000       10.000
Inst2_ECLKSYNCB     System        ECLKSYNCB     ECLKO     eclkfb       0.000       10.000
Inst3_ECLKSYNCB     System        ECLKSYNCB     ECLKO     eclko        0.000       10.000
Inst4_CLKDIVF       System        CLKDIVF       CDIVX     sclk         0.000       10.000
=========================================================================================


<a name=endingSlack16>Ending Points with Worst Slack</a>
******************************

                                   Starting                                                        Required           
Instance                           Reference     Type          Pin       Net                       Time         Slack 
                                   Clock                                                                              
----------------------------------------------------------------------------------------------------------------------
Inst_gddr_sync.cs_gddr_sync[0]     System        FD1P3DX       D         N_120_i                   9.946        8.848 
Inst_gddr_sync.stop_assert[1]      System        FD1S3DX       D         stop_assert_4[1]          9.946        8.848 
Inst_gddr_sync.stop_assert[2]      System        FD1S3DX       D         stop_assert_4[2]          9.946        8.848 
Inst_gddr_sync.cs_gddr_sync[2]     System        FD1P3DX       D         N_145                     9.946        8.950 
Inst_gddr_sync.reset_flag          System        FD1P3DX       SP        reset_flag_1_sqmuxa_i     9.806        9.416 
Inst_gddr_sync.stop_assert[0]      System        FD1S3DX       D         stop_assert_4[0]          9.946        9.556 
Inst1_EHXPLLL                      System        EHXPLLL       CLKFB     eclkfb                    10.000       10.000
Inst2_ECLKSYNCB                    System        ECLKSYNCB     ECLKI     clkop                     10.000       10.000
Inst3_ECLKSYNCB                    System        ECLKSYNCB     ECLKI     clkos                     10.000       10.000
Inst4_CLKDIVF                      System        CLKDIVF       CLKI      eclko                     10.000       10.000
======================================================================================================================



<a name=worstPaths17>Worst Path Information</a>
<a href="D:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\syn_results\ip_gddr71rx.srr:srsfD:\RD_Work_Area\rd1093_display_interface\rd1093\source\verilog\ecp5\clarity\ecp5_ip\ip_gddr71rx\syn_results\ip_gddr71rx.srs:fp:27677:28640:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.054
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.946

    - Propagation time:                      1.098
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 8.848

    Number of logic level(s):                2
    Starting point:                          Inst1_EHXPLLL / LOCK
    Ending point:                            Inst_gddr_sync.cs_gddr_sync[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            ip_gddr71rx|sync_clk [rising] on pin CK

Instance / Net                                          Pin      Pin               Arrival     No. of    
Name                                       Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
Inst1_EHXPLLL                              EHXPLLL      LOCK     Out     0.000     0.000       -         
lock_chk                                   Net          -        -       -         -           5         
Inst_gddr_sync.stop_assert_RNIRNT61[0]     ORCALUT4     D        In      0.000     0.000       -         
Inst_gddr_sync.stop_assert_RNIRNT61[0]     ORCALUT4     Z        Out     0.708     0.708       -         
CO0_0                                      Net          -        -       -         -           3         
Inst_gddr_sync.cs_gddr_sync_RNO[0]         ORCALUT4     A        In      0.000     0.708       -         
Inst_gddr_sync.cs_gddr_sync_RNO[0]         ORCALUT4     Z        Out     0.390     1.098       -         
N_120_i                                    Net          -        -       -         -           1         
Inst_gddr_sync.cs_gddr_sync[0]             FD1P3DX      D        In      0.000     1.098       -         
=========================================================================================================



##### END OF TIMING REPORT #####]

---------------------------------------
<a name=resourceUsage18>Resource Usage Report</a>
Part: lfe5um_25f-6

Register bits: 12 of 24288 (0%)
PIC Latch:       0
I/O cells:       5


Details:
FD1P3DX:        4
FD1S3BX:        1
FD1S3DX:        7
GSR:            1
IB:             5
INV:            1
ORCALUT4:       22
PUR:            1
VHI:            2
VLO:            2
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 54MB peak: 144MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Thu Nov 06 18:07:31 2014

###########################################################]

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